Technical Field
The present disclosure relates to switched-mode power supplies (SMPS), and more specifically to the generation of a duty cycle for controlling a power switch of the SMPS.
Description of the Related Art
FIG. 1 is a block diagram of an exemplary buck SMPS. It comprises an inductor L connected in series between a load RL and a high-side switch SWH. The switch SWH is further connected to a supply line Vdd, and the load RL is further connected to a ground line Vss. A filter capacitor C is connected in parallel with the load RL. A low-side switch SWL couples the high-side switch SWH to line Vss.
As shown, the switches SWH and SWL may be N-MOS transistors driven independently by respective signals HI, LO. The signals HI, LO are produced by a driver circuit 10 based on a pulse-width modulation signal (PWM) generated by a circuit 12. Circuit 12 may generate the PWM signal from a clock signal CK and a control voltage Vctrl.
The driver circuit 10 is usually configured to drive transistors SWH and SWL in phase opposition. In simpler SMPS devices, the low-side transistor SWL may be replaced by a freewheel diode.
FIG. 2A is a simplified circuit diagram of an exemplary PWM circuit 12. A ramp generator includes a capacitor Cr charged from the line Vdd through a constant current source Ir. The clock signal CK drives a switch SWr to periodically discharge the capacitor Cr. In this configuration, the clock signal CK is applied to the switch SWr in the form of short pulses that are sufficiently wide to cause a full discharge of the capacitor Cr.
The ramp voltage Vr is taken from the node between the current source Ir and the capacitor Cr. The voltage Vr is applied to an inverting input of a comparator 14. The non-inverting input of the comparator receives the control voltage Vctrl. The output of the comparator produces the PWM signal with a duty-cycle set by the control voltage Vctrl.
FIG. 2B illustrates an exemplary evolution of signals CK, Vr and PWM for a linearly rising voltage Vctrl. As voltage Vctrl increases, the duty-cycle of signal PWM increases proportionally. The ramp Vr reaches a peak voltage Vpk equal to Ir·Tck/Cr (assuming that the fall time of the ramp is negligible), where Tck is the period of clock CK. Voltage Vpk thus defines the variation range of voltage Vctrl for producing a duty cycle between 0 and 100%. In practice, duty cycles of 0% and 100% are not reached.
The SMPS structure of FIG. 1 may be used in a control loop for regulating the voltage VL across the load RL. Then, as shown, the control voltage Vctrl may be produced as an error voltage based on the difference between the load voltage VL and a target value Vref. In a stable operation of the regulated SMPS, the duty-cycle assumes an average value of Ton/Tck=VL/Vdd (assuming that the voltage drops in the transistors and inductor are negligible), where Ton is the conduction time of the high-side transistor SWH within each clock period Tck.
When the power consumed by the load RL decreases below a threshold, the SMPS enters a discontinuous operating mode, where the current IL in the inductor L reaches zero. Such an operation mode may cause difficulties in maintaining good energy efficiency.